module sync (clock, d_i, v_i, credit_out, clear_to_send,reset);
	parameter mem_depth = 32;
	parameter addr_sz = 6;
	parameter mem_width = 34;
	input clock;
	input [33:0] d_i;
	input v_i;
	input reset;
	input clear_to_send;
	output wire credit_out;
	reg [mem_width-1:0] mem [mem_depth-1:0];
	reg [addr_sz-1:0] addr;
	reg [mem_depth:0] counter;
	assign credit_out = (v_i)&(clear_to_send);
	always @(posedge clock or negedge reset) begin
		if (~reset) begin
			for(counter = 0; counter < mem_depth; counter=counter+1) begin
				mem[counter] <= 35;
			end
			addr <= 0; 
		end

		else begin
			if (credit_out) begin
				addr <= addr + 1;
				mem[addr] <= d_i;
			end

		end
	end


		
	
endmodule 
